Cadence Digital, Custom/Analog Design Flows certified for Samsung Foundry’s SF2 and SF3 process technologies

Cadence Digital, Custom/Analog Design Flows certified for Samsung Foundry’s SF2 and SF3 process technologies

Cadence Design Systems, Inc. announced that its digital and custom/analog streams have been certified for Samsung Foundry’s SF2 and SF3 process technologies. The two companies also collaborated to create new process design kits (PDKs) that simplify mobile, automotive, AI and hyperscale IC design on these latest nodes. Joint customers are actively developing SF2 and SF3 based designs using the Cadence® flows.

Cadence Digital Tools optimized for SF2 and SF3 technologies

Cadence’s comprehensive Cadence RTL-to-GDS design flow supporting Samsung’s SF2 and SF3 technologies provides optimal power, performance, and surface area (PPA). Flow includes Genus™ Synthesis Solution, Modus DFT Software Solution, Innovus™ Implementation System, Quantus™ Extraction Solution and Quantus Field Solver, Tempus™ Timing Signoff Solution and Tempus ECO Option, Pegasus™ Verification System, Liberate™ Characterization Portfolio, Voltus™ IC Power Integrity solution and the Cadence Cerebrus™ Intelligent Chip Explorer.

With the certified power, customers can access several features that facilitate the design of ICs on advanced nodes, such as support for cell swapping, which allows designers to align cell pins for direct connections to save routing resources; support for mixed-row solutions in various combinations to maximize area-based design rules; the ability to place and refine tracks using mask-shifted cells and horizontal half-track shifted cells to reduce displacement; support for several rectilinear standard cells to achieve higher density; and reduced IR drop through the insertion of enhanced, trim-aware staples.

Cadence Custom/Analog Tools optimized for SF2 and SF3 technologies

Custom and analog cadence tools optimized for Samsung’s SF3 and SF2 nodes include the AI-based Virtuoso® Studio design tools—Virtuoso Schematic Editor, Virtuoso ADE Suite, and Cadence Virtuoso Layout Suite—the Spectre® Simulation Platform—Spectre X Simulator, Specter FX and Specter RF—as well as the Voltus™-XFi Custom Power Integrity solution.

The custom/analog design tools provide customers with several benefits, such as better angle simulation management, statistical analysis, design centering, and circuit optimization; support for parallel operations on modern compute farms and private and public cloud configurations; better performance and scalability across the layout environment; mixed-signal OpenAccess design kits for seamless integration with the Innovus implementation place-and-route engines for improved quality of results; summarized EM-IR information, which highlights violations and details resistance value, metal layer, latitude and longitude information; and feedback regarding circuit performance and reliability.

“Through our latest partnership with Cadence, we have seen early customers improve productivity with Cadence-certified design flows and our advanced SF2 and SF3 process technologies,” said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “With the new PDKs, we are making it easier for developers of next-generation mobile, automotive, AI and hyperscale designs to adopt our technologies and bring innovations to market faster.”

“Cadence’s R&D team worked tirelessly with the Samsung Foundry team to refine our digital and custom/analog flows for Samsung’s SF2 and SF3 process technologies, delivering a wide range of benefits that enable customers to design much more efficiently said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “Our digital stream offers PPA benefits, and our custom/analog stream, anchored by Virtuoso Studio, sets a new standard for custom IP creation, enabling our mutual customers to push the boundaries of innovation with the SF2 and SF3 process technologies of Samsung.”

The Cadence digital and custom/analog flows support the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.

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