Samsung unveils refined 3nm and performance-enhanced 4nm nodes at VLSI Symposium
Samsung Foundry will detail its second-generation 3nm-class fabrication technology and its performance-enhanced 4nm-class fabrication process at the upcoming Symposium on VLSI Technology and Circuits in 2023 in Kyoto, Japan. Both technologies are important to the chip contract maker, as SF3 (3GAP) promises to deliver tangible improvements for mobile and SoCs, while SF4X (N4HPC) is specifically designed for the most demanding high-performance computing (HPC) applications.
2nd Generation 3 nm Node with GAA Transistors
Samsung’s forthcoming SF3 (3GAP) process technology is an improved version of the company’s SF3E (3GAE) manufacturing process and relies on its second-generation gate-all-round transistors — which the company calls Multi-Bridge-Channel Field-Effect Transistors (MBCFETs). ). The node promises additional process optimizations, although the foundry prefers not to compare SF3 with SF3E. Compared to its direct predecessor, SF4 (4LPP, 4nm class, low power plus), SF3 claims a 22% performance increase at the same power and complexity or a 34% power reduction at the same clocks and number of transistors, as well as a 21% logical area reduction. Although it is unclear if the company has achieved scaling for SRAM and analog circuitry.
In addition, Samsung claims that SF3 will provide additional design flexibility enabled by different nanosheet (NS) channel widths of the MBCFET device within the same cell type. Oddly enough, variable channel width has been a feature of GAA transistors that has been talked about for years, so Samsung’s way of phrasing it in the context of SF3 could mean that SF3E doesn’t support it.
Samsung’s simplest 4nm node: SF4E (IEDM 2021)
To date, neither Samsung LSI, the conglomerate’s chip development arm, nor other Samsung Foundry customers have formally introduced a single highly complex processor mass produced on SF3E/3GAE process technology. In fact, according to TrendForce, it appears that the only publicly recognized application using the industry’s first 3nm-class fabrication process is a cryptocurrency mining chip. This is not surprising, since the use of Samsung’s ‘early’ nodes is usually quite limited.
In contrast, Samsung’s “plus” technologies are typically used by a wide range of customers, so the company’s SF3 process (3GAP) is likely to see much higher volumes when it becomes available sometime in 2024.
SF4X for ultra-high performance applications
In addition to SF3, which is designed for various possible use cases, Samsung Foundry is preparing its SF4X (4HPC, 4 nm-class high-performance computing), designed for performance-demanding applications such as data center-oriented CPUs and GPUs.
To tackle such chips, Samsung’s SF4X offers a 10% performance boost coupled with a 23% power reduction. Samsung does not explicitly specify which process node the comparison is being made against, but presumably this is against their standard SF4 (4LPP) manufacturing technology. To achieve this, Samsung redesigned the source and drain of transistors after a reassessment of their voltages (presumably under high load), performed further co-optimization of transistor-level design technology (T-DTCO), and developed a new middle-of-line (MOL) introduced. ) regulation.
The new MOL enabled SF4X to provide a silicon-proven CPU minimum voltage (Vmin) of 60 mV, a 10% decrease in off-state current variation (IDDQ), guaranteed high voltage (Vdd) operation at over 1V with no loss of performance, and an improved SRAM process margin.
Samsung’s SF4X will rival TSMC’s N4P and N4X nodes, expected in 2024 and 2025, respectively. Based on claim specs alone, it’s hard to say which technology will provide the best combination of performance, power, transistor density, efficiency, and cost. That said, SF4X will be Samsung’s first node in recent years designed specifically with HPC in mind, implying that Samsung has (or expects) enough customer demand to make it worth their time.